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d a t a sh eet product speci?cation supersedes data of 2003 may 15 2003 oct 30 integrated circuits 74hct9046a pll with band gap controlled vco
2003 oct 30 2 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a features operation power supply voltage range from 4.5 to 5.5 v low power consumption inhibit control for on/off keying and for low standby power consumption centre frequency up to 17 mhz (typical) at v cc = 5.5 v choice of two phase comparators: C pc1: exclusive-or C pc2: edge-triggered jk flip-flop. no dead zone of pc2 charge pump output on pc2, whose current is set by an external resistor r b centre frequency tolerance 10% excellent voltage controlled oscillator (vco) linearity low frequency drift with supply voltage and temperature variations on-chip band gap reference glitch free operation of vco, even at very low frequencies zero voltage offset due to op-amp buffering esd protection: C hbm eia/jesd22-a114-a exceeds 2000 v C mm eia/jesd22-a115-a exceeds 200 v. applications fm modulation and demodulation where a small centre frequency tolerance is essential frequency synthesis and multiplication where a low jitter is required (e.g. video picture-in-picture) frequency discrimination tone decoding data synchronization and conditioning voltage-to-frequency conversion motor-speed control. general description the 74hct9046a is a high-speed si-gate cmos device. it is specified in compliance with jedec standard no 7a. quick reference data gnd = 0 v; t amb =25 c; t r =t f 6ns. notes 1. c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i n+ s (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in volts; n = total load switching outputs; s (c l v cc 2 f o ) = sum of the outputs. 2. applies to the phase comparator section only (pin inh = high). for power dissipation of the vco and demodulator sections, see figs 26 to 28. symbol parameter conditions typical unit f c vco centre frequency c1 = 40 pf; r 1=3k w ; v cc = 5 v 16 mhz c i input capacitance 3.5 pf c pd power dissipation capacitance per package notes 1 and 2 20 pf
2003 oct 30 3 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a ordering information type number package pins package material code 74hct9046an 16 dip16 plastic sot38-1 74hct9046ad 16 so16 plastic sot109-1 74HCT9046APW 16 tssop16 plastic sot403-1 pinning pin symbol description 1 gnd ground (0 v) of phase comparators 2 pc1_out/ pcp_out phase comparator 1 output or phase comparator pulse output 3 comp_in comparator input 4 vco_out vco output 5 inh inhibit input 6 c1a capacitor c1 connection a 7 c1b capacitor c1 connection b 8 gnd ground (0 v) vco 9 vco_in vco input 10 dem_out demodulator output 11 r1 resistor r1 connection 12 r2 resistor r2 connection 13 pc2_out phase comparator 2 output; current source adjustable with r b 14 sig_in signal input 15 rb bias resistor (r b ) connection 16 v cc supply voltage fig.1 pin configuration. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 gnd pc1_out/ pcp_out comp_in vco_out c1b c1a gnd vco_in dem_out r2 r1 pc2_out sig_in v cc rb 9046a mbd037 inh
2003 oct 30 4 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a logic and functional symbols and diagrams fig.2 logic symbol. mbd038 pc1_out/ pcp_out vco_out c1a c1b vco_in dem_out r2 r1 sig_in inh vco 6 7 11 12 9 5 4 10 2 13 3 14 15 pc2_out f comp_in rb fig.3 iec logic symbol. mbd039 sig_in inh 6 7 11 12 9 5 4 10 2 13 3 14 15 f comp_in pll 9046a pc1_out/ pcp_out vco_out c1a c1b vco_in dem_out r2 r1 pc2_out rb fig.4 block diagram. phase comparator 2 13 phase comparator 1 2 15 sig_in comp_in c1a c1b f out f in v cc dem_out inh vco_in r2 12 11 314 16 4 7 6 5109 gnd 8 gnd 1 c1 9046a vco r s r1 r4 r3 c2 pc2_out mbd040 pc1_out/ pcp_out vco_out r2 r1 rb r b
2003 oct 30 5 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... h andbook, full pagewidth mbd102 pcp dq cp q r d logic 1 dq cp q r d logic 1 down up charge pump v ref2 v ref2 v ref2 v ref1 v ref1 pc1_out/ pcp_out pc2_out b r b rb c2 r4 2 13 r3 15 comp_in sig_in 314 pc1 band gap 5 inh 9 vco dem_out vco_out c1b c1a 7 64 c1 12 r2 11 r1 10 r f out f in r2 r1 s vco_in r3' = r /17 r3' (1) (1) fig.5 logic diagram.
2003 oct 30 6 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a functional description the 74hct9046a is a phase-locked-loop circuit that comprises a linear vco and two different phase comparators (pc1 and pc2) with a common signal input amplifier and a common comparator input (see fig.4). the signal input can be directly coupled to large voltage signals (cmos level), or indirectly coupled (with a series capacitor) to small voltage signals. a self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. with a passive low-pass filter, the 74hct9046a forms a second-order loop pll. the principle of this phase-locked-loop is based on the familiar 74hct4046a. however extra features are built-in, allowing very high-performance phase-locked-loop applications. this is done, at the expense of pc3, which is skipped in this 74hct9046a. the pc2 is equipped with a current source output stage here. further a band gap is applied for all internal references, allowing a small centre frequency tolerance. the details are summed up in the next section: differences with respect to the familiar 74hct4046a. if one is familiar with the 74hct4046a already, it will do to read this section only. differences with respect to the familiar 74hct4046a a centre frequency tolerance of maximum 10%. the on board band gap sets the internal references resulting in a minimal frequency shift at supply voltage variations and temperature variations. the value of the frequency offset is determined by an internal reference voltage of 2.5 v instead of v cc - 0.7 v. in this way the offset frequency will not shift over the supply voltage range. a current switch charge pump output on pin pc2_out allows a virtually ideal performance of pc2. the gain of pc2 is independent of the voltage across the low-pass filter. further a passive low-pass filter in the loop achieves an active performance. the influence of the parasitic capacitance of the pc2 output plays no role here, resulting in a true correspondence of the output correction pulse and the phase difference even up to phase differences as small as a few nanoseconds. because of its linear performance without dead zone, higher impedance values for the filter, hence lower c-values, can now be chosen. correct operation will not be influenced by parasitic capacitances as in the instance with voltage source output of the 4046a. no pc3 on pin rb but instead a resistor connected to gnd, which sets the load/unload currents of the charge pump (pc2). extra gnd pin 1 to allow an excellent fm demodulator performance even at 10 mhz and higher. combined function of pin pc1_out/pcp_out. if pin rb is connected to v cc (no bias resistor r b ) pin pc1_out/pcp_out has its familiar function viz. output of pc1. if at pin rb a resistor (r b ) is connected to gnd it is assumed that pc2 has been chosen as phase comparator. connection of r b is sensed by internal circuitry and this changes the function of pin pc1_out/pcp_out into a lock detect output (pcp_out) with the same characteristics as pcp_out of pin 1 of the 74hct4046a. the inhibit function differs. for the hct4046a a high level at the inhibit input (pin inh) disables the vco and demodulator, while a low level turns both on. for the 74hct9046a a high level on the inhibit input disables the whole circuit to minimize standby power consumption. vco the vco requires one external capacitor c1 (between pins c1a and c1b) and one external resistor r1 (between pins r1 and gnd) or two external resistors r1 and r2 (between pins r1 and gnd, and r2 and gnd). resistor r1 and capacitor c1 determine the frequency range of the vco. resistor r2 enables the vco to have a frequency offset if required (see fig.5). the high input impedance of the vco simplifies the design of the low-pass filters by giving the designer a wide choice of resistor/capacitor ranges. in order not to load the low-pass filter, a demodulator output of the vco input voltage is provided at pin dem_out. the dem_out voltage equals that of the vco input. if dem_out is used, a load resistor (r s ) should be connected from pin dem_out to gnd; if unused, dem_out should be left open. the vco output (pin vco_out) can be connected directly to the comparator input (pin comp_in), or connected via a frequency divider. the output signal has a duty factor of 50% (maximum expected deviation 1%), if the vco input is held at a constant dc level. a low level at the inhibit input (pin inh) enables the vco and demodulator, while a high level turns both off to minimize standby power consumption.
2003 oct 30 7 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a phase comparators the signal input (pin sig_in) can be directly coupled to the self-biasing amplifier at pin sig_in, provided that the signal swing is between the standard hc family input logic levels. capacitive coupling is required for signals with smaller swings. p hase comparator 1 (pc1) this circuit is an exclusive-or network. the signal and comparator input frequencies (f i ) must have a 50% duty factor to obtain the maximum locking range. the transfer characteristic of pc1, assuming ripple (f r =2f i ) is suppressed, is: where: v dem_out is the demodulator output at pin dem_out. v dem_out =v pc1_out (via low-pass). the phase comparator gain is: the average output voltage from pc1, fed to the vco input via the low-pass filter and seen at the demodulator output at pin dem_out (v dem_out ), is the resultant of the phase differences of signals (sig_in) and the comparator input (comp_in) as shown in fig.6. the average of v dem_out is equal to 0.5v cc when there is no signal or noise at sig_in and with this input the vco oscillates at the centre frequency (f c ). typical waveforms for the pc1 loop locked at f c are shown in fig.7. this figure also shows the actual waveforms across the vco capacitor at pins c1a and c1b (v c1a and v c1b ) to show the relation between these ramps and the vco_out voltage. the frequency capture range (2f c ) is defined as the frequency range of input signals on which the pll will lock if it was initially out-of-lock. the frequency lock range (2f l ) is defined as the frequency range of the input signals on which the loop will stay locked if it was initially in lock. the capture range is smaller or equal to the lock range. with pc1, the capture range depends on the low-pass filter characteristics and can be made as large as the lock range. this configuration remains locked even with very noisy input signals. typical behaviour of this type of phase comparator is that it may lock to input frequencies close to the harmonics of the vco centre frequency. v dem_out v cc p ---------- - f sig_in f comp_in C () = k p v cc p ---------- - vr () = fig.6 phase comparator 1; average output voltage as a function of input phase difference. mbd101 180 o pc_in 0 o 90 o 0.5v 0 v v dem_out(av) cc cc f v dem_out v pc1_out v cc p ---------- - f sig_in f comp_in C () == f pc_in f sig_in f comp_in C () = fig.7 typical waveforms for pll using phase comparator 1; loop-locked at f c . mbd100 pc1_out vco_in v cc gnd vco_out comp_in sign_in c1a c1b v c1a v c1b
2003 oct 30 8 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a p hase comparator 2 (pc2) this is a positive edge-triggered phase and frequency detector. when the pll is using this comparator, the loop is controlled by positive signal transitions and the duty factors of sig_in and comp_in are not important. pc2 comprises two d-type flip-flops, control gating and a 3-state output stage with sink and source transistors acting as current sources, henceforth called charge pump output of pc2. the circuit functions as an up-down counter (see fig.5) where sig_in causes an up-count and comp_in a down count. the current switch charge pump output allows a virtually ideal performance of pc2, due to appliance of some pulse overlap of the up and down signals. see fig.8a. the pump current i p is independent from the supply voltage and is set by the internal band gap reference of 2.5 v. where r b is the external bias resistor between pin rb and ground. the current and voltage transfer function of pc2 are shown in fig.9. the phase comparator gain is: i p 17 2.5 r b ------- - a () = k p i p 2 p ------- ar () = mbd099 r3' i p up down c2 v cc pc2_out vc2_out fig.8 the current switch charge pump output of pc2. a. at every df , even at zero df both switches are closed simultaneously for a short period (typically 15 ns). mbd046 pc2_out c2 v cc i p i p down up d f = f pulse overlap of approximately 15 ns pc_in b. comparable voltage-controlled switch.
2003 oct 30 9 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a handbook, full pagewidth 0 msb306 0 0.5v cc 0 v cc v dem_out(av) i p r 0 f pc_in f pc_in f pc_in = f sig_in - f comp_in + i p - i p - 2 p + 2 p - 2 p + 2 p fig.9 phase comparator 2. two kinds of transfer functions may be regarded: b.the voltage transfer; this transfer can be observed at pc2_out by connecting a resistor (r=10k w ) between pc2_out and 0.5v cc ; . v dem_out v pc2_out 5 4 p ------ - f pc_in == a. the current transfer: pump current i p 2 p ------- f pc_in when the frequencies of sig_in and comp_in are equal but the phase of sig_in leads that of comp_in, the up output driver at pc2_out is held on for a time corresponding to the phase difference ( f pc_in ). when the phase of sig_in lags that of comp_in, the down or sink driver is held on. when the frequency of sig_in is higher than that of comp_in, the source output driver is held on for most of the input signal cycle time and for the remainder of the cycle time both drivers are off (3-state). if the sig_in frequency is lower than the comp_in frequency, then it is the sink driver that is held on for most of the cycle. subsequently the voltage at the capacitor (c2) of the low-pass filter connected to pc2_out varies until the signal and comparator inputs are equal in both phase and frequency. at this stable point the voltage on c2 remains constant as the pc2 output is in 3-state and the vco input at pin 9 is a high impedance. also in this condition the signal at the phase comparator pulse output (pcp_out) has a minimum output pulse width equal to the overlap time, so can be used for indicating a locked condition. thus for pc2 no phase difference exists between sig_in and comp_in over the full frequency range of the vco. moreover, the power dissipation due to the low-pass filter is reduced because both output drivers are off for most of the signal input cycle. it should be noted that the pll lock range for this type of phase comparator is equal to the capture range and is independent of the low-pass filter. with no signal present at sig_in the vco adjust, via pc2, to its lowest frequency. by using current sources as charge pump output on pc2, the dead zone or backlash time could be reduced to zero. also, the pulse widening due to the parasitic output capacitance plays no role here. this enables a linear transfer function, even in the vicinity of the zero crossing. the differences between a voltage switch charge pump and a current switch charge pump are shown in fig.11.
2003 oct 30 10 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a mbd047 sig_in comp_in vco_out high-impedance off-state, (zero current) 15 ns typical up down current at pc2_out pc2_out/vco_in pcp_out pc_in fig.10 timing diagram for pc2. the pulse overlap of the up and down signals (typically 15 ns). fig.11 the response of a locked-loop in the vicinity of the zero crossing of the phase error. h andbook, full pagewidth mbd043 25 2.50 2.75 2.25 vco_in vco_in 025 phase error (ns) (1) (1) (2) 25 2.50 2.75 2.25 025 phase error (ns) a. response with traditional voltage-switch charge-pump pc2_out (74hct4046a). (1) due to parasitic capacitance on pc2_out. (2) backlash time (dead zone). b. response with current switch charge-pump pc2_out as applied in the 74hct9046a.
2003 oct 30 11 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a the design of the low-pass filter is somewhat different when using current sources. the external resistor r3 is no longer present when using pc2 as phase comparator. the current source is set by r b . a simple capacitor behaves as an ideal integrator now, because the capacitor is charged by a constant current. the transfer function of the voltage switch charge pump may be used. in fact it is even more valid, because the transfer function is no longer restricted for small changes only. further the current is independent from both the supply voltage and the voltage across the filter. for one that is familiar with the low-pass filter design of the 74hct4046a a relation may show how r b relates with a fictive series resistance, called r3'. this relation can be derived by assuming first that a voltage controlled switch pc2 of the 74hct4046a is connected to the filter capacitance c2 via this fictive r3' (see fig.8b). then during the pc2 output pulse the charge current equals: with the initial voltage v c2(0) at: 0.5v cc = 2.5 v, as shown before the charge current of the current switch of the 74hct9046a is: hence: using this equivalent resistance r3' for the filter design the voltage can now be expressed as a transfer function of pc2; assuming ripple (f r =f i ) is suppressed, as: again this illustrates the supply voltage independent behaviour of pc2. loop filter component selection examples of pc2 combined with a passive filter are shown in figs 12 and 13. figure 12 shows that pc2 with only a c2 filter behaves as a high-gain filter. for stability the damped version of fig.13 with series resistance r4 is preferred. practical design values for r b are between 25 and 250 k w with r3' = 1.5 to 15 k w for the filter design. higher values for r3' require lower values for the filter capacitance which is very advantageous at low values the loop natural frequency w n . i p v cc v c2 0 () C r3' --------------------------------- = i p 2.5 r3' -------- - = i p 17 2.5 r b ------- - = r3' r b 17 ------ - w () = k pc2 5 4 p ------ - vr () =
2003 oct 30 12 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a mbd045 - 1 w j () f w 1/ output input c2 i p i p 17 r b 1/ t 1 a a t 1 a fig.12 simple loop filter for pc2 without damping. a. t 1 r b 17 ------ - c2 r3' c2 == b. amplitude characteristic: f j w () 1 1a j wt 1 + ----------------------------- 1 j wt 1 ----------- ? = c. pole zero diagram. mbd044 - 1 w j () f m 1 / t 2 w o 1/ t 2 1/ t 1 output input r4 c2 i p i p 17 r b a 1/ t 1 a a fig.13 simple loop filter for pc2 with damping. a. b. amplitude characteristic: c. pole zero diagram. a = dc gain limit, due to leakage. t 1 r b 17 ------ - c2 r3' c2 == t 2 r4 c2 = f j w () 1j wt 2 + 1a j wt 1 + ----------------------------- =
2003 oct 30 13 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a recommended operating conditions limiting values in accordance with the absolute maximum rating system (iec 60134); voltages are referenced to gnd (ground = 0 v). notes 1. for dip16 packages: above 70 c derate linearly with 12 mw/k. 2. for so16 and tssop16 packages: above 70 c derate linearly with 8 mw/k. symbol parameter conditions min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v v i input voltage 0 - v cc v v o output voltage 0 - v cc v t amb operating ambient temperature see dc and ac characteristics - 40 - +85 c - 40 - +125 c t r ,t f input rise and fall times on pin inh v cc = 4.5 v - 6 500 ns symbol parameter conditions min. max. unit v cc supply voltage - 0.5 +7 v i ik input diode current v i <- 0.5 v or v i > v cc + 0.5 v - 20 ma i ok output diode current v o <- 0.5 v or v o > v cc + 0.5 v - 20 ma i o output source or sink current - 0.5 v < v o < v cc + 0.5 v - 25 ma i cc , i gnd v cc or gnd current - 50 ma t stg storage temperature - 65 +150 c p tot total power dissipation t amb = - 40 to +125 c dip16 note 1 - 750 mw so16 and tssop16 note 2 - 500 mw
2003 oct 30 14 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a dc characteristics at recommended operating conditions; voltages are referenced to gnd (groun d=0v). symbol parameter test conditions min. typ. max. unit other v cc (v) t amb =25 c p hase comparator section v ih high-level input voltage on pins sig_in and comp_in dc coupled 4.5 3.15 2.4 - v v il low-level input voltage on pins sig_in and comp_in dc coupled 4.5 - 2.1 1.35 v v oh high-level output voltage on pins pcp_out and pcn_out v i =v ih or v il i o = - 20 m a 4.5 4.4 4.5 - v i o = - 4.0 ma 4.5 3.98 4.32 - v v ol low-level output voltage on pins pcp_out and pcn_out v i =v ih or v il i o =20 m a 4.5 - 0 0.1 v i o = 4.0 ma 4.5 - 0.15 0.26 v i li input leakage current in pins sig_in and comp_in v cc or gnd 5.5 -- 30 m a i oz 3-state off-state current in pin pc2_out v i =v ih or v il ; v o =v cc or gnd 5.5 -- 0.5 m a r i input resistance sig_in, comp_in v i at self-bias operating point; d v i = 0.5 v; see figs 14 to 16 4.5 - 250 - k w r b bias resistance 4.5 25 - 250 k w i p charge pump current r b =40k w 4.5 0.53 1.06 2.12 ma vco section v ih high-level input voltage on pin inh dc coupled 4.5 to 5.5 2.0 1.6 - v v il low-level input voltage on pin inh dc coupled 4.5 to 5.5 - 1.2 0.8 v v oh high-level output voltage on pin vco_out v i =v ih or v il i o = - 20 m a 4.5 4.4 4.5 - v i o = - 4.0 ma 4.5 3.98 4.32 - v v ol low-level output voltage on pin vco_out v i =v ih or v il i o =20 m a 4.5 - 0 0.1 v i o = 4.0 ma 4.5 - 0.15 0.26 v v ol low-level output voltage on pins c1a and c1b v i =v ih or v il ; i o = 4.0 ma 4.5 -- 0.40 v i li input leakage current in pins inh and vco_in v cc or gnd 5.5 -- 0.1 m a
2003 oct 30 15 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a r1 resistor value 4.5 3 - 300 k w r2 resistor value 4.5 3 - 300 k w c1 capacitance 4.5 40 - no limit pf v vco_in operating voltage on pin vco_in over the range speci?ed for r1 4.5 1.1 - 3.4 v 5.0 1.1 - 3.9 v 5.5 1.1 - 4.4 v d emodulator section r s resistor value at r s > 300 k w the leakage current can in?uence v dem_out 4.5 50 - 300 k w v off offset voltage vco_in to v dem_out v i =v vco_in = 0.5v cc ; values taken over r s range, see fig.17 4.5 - 20 - mv r dyn dynamic output resistance at dem_out v dem_out = 0.5v cc 4.5 - 25 -w g eneral i cc quiescent supply current (disabled) pin inh at v cc 5.5 -- 8.0 m a d i cc additional quiescent supply current per input pin other inputs at v cc or gnd; v i =v cc - 2.1 v 4.5 - 100 360 m a t amb = - 40 to +85 c p hase comparator section v ih high-level input voltage on pins sig_in and comp_in dc coupled 4.5 3.15 -- v v il low-level input voltage on pins sig_in and comp_in dc coupled 4.5 -- 1.35 v v oh high-level output voltage on pins pcp_out and pcn_out v i =v ih or v il i o = - 20 m a 4.5 4.4 -- v i o = - 4.0 ma 4.5 3.84 -- v v ol low-level output voltage on pins pcp_out and pcn_out v i =v ih or v il i o =20 m a 4.5 -- 0.1 v i o = 4.0 ma 4.5 -- 0.33 v i li input leakage current in pins sig_in and comp_in v cc or gnd 5.5 -- 38 m a i oz 3-state off-state current pc2_out v i =v ih or v il ; v o =v cc or gnd 5.5 -- 5.0 m a symbol parameter test conditions min. typ. max. unit other v cc (v)
2003 oct 30 16 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a vco section v ih high-level input voltage on pin inh dc coupled 4.5 to 5.5 2.0 -- v v il low-level input voltage on pin inh dc coupled 4.5 to 5.5 -- 0.8 v v oh high-level output voltage on pin vco_out v i =v ih or v il i o = - 20 m a 4.5 4.4 -- v i o = - 4.0 ma 4.5 3.84 -- v v ol low-level output voltage on pin vco_out v i =v ih or v il i o =20 m a 4.5 -- 0.1 v i o = 4.0 ma 4.5 -- 0.33 v v ol low-level output voltage on pins c1a and c1b v i =v ih or v il ; i o = 4.0 ma 4.5 -- 0.47 v i li input leakage current in pins inh and vco_in v cc or gnd 5.5 -- 1.0 m a q uiescent supply current i cc quiescent supply current (disabled) pin inh at v cc 5.5 -- 80.0 m a d i cc additional quiescent supply current per input pin other inputs at v cc or gnd; v i =v cc - 2.1 v 4.5 -- 450 m a t amb = - 40 to +125 c p hase comparator section v ih high-level input voltage on pins sig_in and comp_in dc coupled 4.5 3.15 -- v v il low-level input voltage on pins sig_in and comp_in dc coupled 4.5 -- 1.35 v v oh high-level output voltage on pins pcp_out and pcn_out v i =v ih or v il i o = - 20 m a 4.5 4.4 -- v i o = - 4.0 ma 4.5 3.7 -- v v ol low-level output voltage on pins pcp_out and pcn_out v i =v ih or v il i o =20 m a 4.5 -- 0.1 v i o = 4.0 ma 4.5 -- 0.4 v i li input leakage current in pins sig_in and comp_in v cc or gnd 5.5 -- 45 m a i oz 3-state off-state current in pin pc2_out v i =v ih or v il ; v o =v cc or gnd 5.5 -- 10.0 m a symbol parameter test conditions min. typ. max. unit other v cc (v)
2003 oct 30 17 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a vco section v ih high-level input voltage on pin inh dc coupled 4.5 to 5.5 2.0 -- v v il low-level input voltage on pin inh dc coupled 4.5 to 5.5 -- 0.8 v v oh high-level output voltage on pin vco_out v i =v ih or v il i o = - 20 m a 4.5 4.4 -- v i o = - 4.0 ma 4.5 3.7 -- v v ol low-level output voltage on pin vco_out v i =v ih or v il i o =20 m a 4.5 -- 0.1 v i o = 4.0 ma 4.5 -- 0.4 v v ol low-level output voltage on pins c1a and c1b v i =v ih or v il ; i o = 4.0 ma 4.5 -- 0.54 v i li input leakage current in pins inh and vco_in v cc or gnd 5.5 -- 1.0 m a g eneral i cc quiescent supply current (disabled) pin inh at v cc 5.5 -- 160.0 m a d i cc additional quiescent supply current per input pin other inputs at v cc or gnd; v i =v cc - 2.1 v 4.5 -- 490 m a symbol parameter test conditions min. typ. max. unit other v cc (v)
2003 oct 30 18 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a fig.14 typical input resistance curve at sig_in, comp_in. mbd108 self-bias operating point v i d v i i i fig.15 input resistance at sig_in; comp_in with d v i = 0.5 v at self-bias point. 800 600 200 0 400 mga956 - 1 v (v) i (0.5 v cc ) - 0.25 0.5 v cc (0.5 v cc ) + 0.25 r i (k ) w 5.5 v v cc = 4.5 v fig.16 input current at sig_in; comp_in with d v i = 0.5 v at self-bias point. 5 5 0 mga957 v (v) i (0.5 v cc ) - 0.25 0.5 v cc (0.5 v cc ) + 0.25 i i ( a) m 4.5 v v cc = 5.5v 5.5 v 4.5 v fig.17 offset voltage at demodulator output as a function of vco_in and r s . 40 - 40 0 mga958 (0.5 v cc ) - 2 (0.5 v cc ) + 2 0.5 v cc - 20 20 60 v off (mv) v vco_in (v) 5.5 v 4.5 v v = cc ___ r s =50k w . - - - r s = 300 k w .
2003 oct 30 19 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a ac characteristics gnd = 0 v; t r =t f = 6 ns; c l =50pf. symbol parameter test condition min. typ. max. unit waveforms v cc (v) t amb =25 c p hase comparator section t phl /t plh propagation delay sig_in, comp_in to pc1_out fig.18 4.5 - 23 40 ns propagation delay sig_in, comp_in to pcp_out fig.18 4.5 - 35 68 ns t pzh /t pzl 3 - state output enable time sig_in, comp_in to pc2_out fig.19 4.5 - 30 56 ns t phz /t plz 3 - state output enable time sig_in, comp_in to pc2_out fig.19 4.5 - 36 65 ns t thl /t tlh output transition time fig.18 4.5 - 715ns v i(p-p) input sensitivity at pin sign_in or comp_in (peak-to-peak value) ac coupled; f i = 1 mhz 4.5 - 15 - mv vco section d f c centre frequency tolerance v vco_in = 3.9 v; r1 = 10 k w ; r2 = 10 k w ; c1 = 1 nf 5.0 - 10 - +10 % f c vco centre frequency duty factor = 50%; v vco_in = 0.5v cc ; r1 = 4.3 k w ; r2 = ; c1 = 40 pf; figs 23 and 31 4.5 11.0 15.0 - mhz d f vco vco frequency linearity r1 = 100 k w ; r2 = ; c1 = 100 pf; figs 24 and 25 4.5 - 0.4 - % d vco duty factor at vco_out 4.5 - 50 - %
2003 oct 30 20 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a t amb = - 40 to +85 c p hase comparator section t phl /t plh propagation delay sig_in, comp_in to pc1_out fig.18 4.5 -- 50 ns propagation delay sig_in, comp_in to pcp_out fig.18 4.5 -- 85 ns t pzh /t pzl 3 - state output enable time sig_in, comp_in to pc2_out fig.19 4.5 -- 70 ns t phz /t plz 3 - state output enable time sig_in, comp_in to pc2_out fig.19 4.5 -- 81 ns t thl /t tlh output transition time fig.18 4.5 -- 19 ns vco section d f/t frequency stability with temperature change v vco_in = 0.5v cc ; recommended range: r1 = 10 k w ; r2 = 10 k w ; c1 = 1 nf; see figs 20 to 22 4.5 0.06 -- %/k t amb = - 40 to +125 c p hase comparator section t phl /t plh propagation delay sig_in, comp_in to pc1_out fig.18 4.5 -- 60 ns propagation delay sig_in, comp_in to pcp_out fig.18 4.5 -- 102 ns t pzh /t pzl 3 - state output enable time sig_in, comp_in to pc2_out fig.19 4.5 -- 84 ns t phz /t plz 3 - state output enable time sig_in, comp_in to pc2_out fig.19 4.5 -- 98 ns t thl /t tlh output transition time fig.18 4.5 -- 22 ns symbol parameter test condition min. typ. max. unit waveforms v cc (v)
2003 oct 30 21 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a fig.18 waveforms showing input (sig_in and comp_in) to output (pcp_out and pc1_out) propagation delays and the output transition times. mbd106 t phl t thl t plh t tlh sig_in, comp_in inputs pcp_out, pc1_out outputs v m v m v m = 0.5v cc ; v i = gnd to v cc . fig.19 waveforms showing the 3-state enable and disable times for pc2_out. mga941 t plz t pzh t phz 10% 90% t pzl sig_in input comp_in input pc2_out output m v m v m v v m = 0.5v cc ; v i = gnd to v cc .
2003 oct 30 22 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a 50 0 50 150 20 10 10 20 0 mbd115 100 d f (%) 5.5 v 4.5 v v = cc t ( c) amb o fig.20 frequency stability of the vco as a function of ambient temperature with supply voltage as a parameter. mbd116 t ( c) amb 0 f (%) o 150 100 50 0 50 15 10 5 5 10 15 d 5.5 v 4.5 v v = cc b. r1 = 10 k w ; r2 = ; c1 = 100 pf. a. r1 = 3 k w ; r2 = ; c1 = 100 pf. 50 0 50 150 10 5 5 10 0 mbd124 100 d f (%) 5.5 v 4.5 v v = cc t ( c) amb o fig.21 frequency stability of the vco as a function of ambient temperature with supply voltage as a parameter. mbd117 t ( c) amb 0 f (%) o 150 100 50 0 50 20 15 10 5 10 15 d 5.5 v 4.5 v v = cc 5 b. r1 = ; r2 = 3 k w ; c1 = 100 pf. a. r1 = 300 k w ; r2 = ; c1 = 100 pf.
2003 oct 30 23 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a mbd118 t ( c) amb 0 f (%) o 150 100 50 0 50 12 8 4 4 8 d 5.5 v 4.5 v v = cc fig.22 frequency stability of the vco as a function of ambient temperature with supply voltage as a parameter. mbd119 t ( c) amb 0 f (%) o 150 100 50 0 50 10 5 5 10 d 5.5 v 4.5 v v = cc b. r1 = ; r2 = 300 k w ; c1 = 100 pf. a. r1 = ; r2 = 10 k w ; c1 = 100 pf.
2003 oct 30 24 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a fig.23 graphs showing vco frequency as a function of the vco input voltage (v vco_in ). a. r1 = 4.3 k w ; c1 = 39 pf. b. r1 = 4.3 k w ; c1 = 100 nf. c. r1 = 300 k w ; c1 = 39 pf. d. r1 = 300 k w ; c1 = 100 nf. handbook, halfpage 0246 800 600 200 0 400 mbd120 f vco (khz) v = 5.5 v cc 4.5 v v vco_in (v) handbook, halfpage 0246 400 300 100 0 200 mbd111 f vco (hz) frequency frequency 4.5 v 5.5 v v = cc v vco_in (v) 0246 30 10 0 20 mbd112 v vco_in (v) f vco (mhz) 5.5 v 4.5 v v = cc 0246 30 10 0 20 mbd113 f vco (khz) 5.5 v 4.5 v v = cc v vco_in (v)
2003 oct 30 25 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a fig.24 definition of vco frequency linearity: d v = 0.5 v over the v cc range. mga937 - 1 f (mhz) max f 1 min 0.5 v cc f' c f c f 2 v vco_in (v) v v f c f 1 f 2 + 2 -------------- - = linearity f c f c C f c --------------- - 100% = fig.25 frequency linearity as a function of r1, c1 and v cc . 4 4 0 1 mbd114 10 10 2 10 3 8 f vco (%) r1 (k w ) c1 = 1 m f 4.5 v 5.5 v c1 = 39 pf 4.5 v 5.5 v r2 = and d v = 0.5 v. fig.26 power dissipation as a function of r1. 300 0 100 mbd121 10 1 1 200 10 2 r1 (k w ) 4.5 v c1 = 1 m f 5.5 v c1 = 39 pf 4.5 v c1 = 39 pf 5.5 v c1 = 1 m f cc v = p d (w) r2 = . fig.27 power dissipation as a function of r2. r1 = . 300 0 100 mbd110 10 1 1 200 10 2 r2 (k w ) p 5.5 v c1 = 39 pf cc 5.5 v 4.5 v c1 = 1 m f 4.5 v c1 = 39 pf v = d (w)
2003 oct 30 26 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a application information this information is a guide for the approximation of values of external components to be used with the 74hct9046a in a phase-locked-loop system. values of the selected components should be within the ranges shown in table 1. table 1 survey of components. fig.28 typical power dissipation as a function of r s . 10 3 mbd109 10 2 10 10 4 p dem (w) r (k w ) s v = cc 5.5 v 4.5 v 10 5 10 3 component value r1 between 3 k w and 300 k w r2 between 3 k w and 300 k w r1 + r2 parallel value >2.7 k w c1 >40 pf table 2 design considerations for vco section. subject phase comparator design consideration vco frequency without extra offset pc1, pc2 vco frequency characteristic. with r2 = and r1 within the range 3k w< r1 < 300 k w , the characteristics of the vco operation will be as shown in fig.29a. (due to r1, c1 time constant a small offset remains when r2 = ). pc1 selection of r1 and c1. given f c , determine the values of r1 and c1 using fig.31. pc2 given f max and f c determine the values of r1 and c1 using fig.31; use fig.33 to obtain 2f l and then use this to calculate f min . vco frequency with extra offset pc1, pc2 vco frequency characteristic. with r1 and r2 within the ranges 3k w< r1 < 300 k w< r2 < 300 k w , the characteristics of the vco operation is as shown in fig.29b. pc1, pc2 selection of r1, r2 and c1. given f c and f l determine the value of product r1c1 by using fig.33. calculate f off from the equation f off =f c - 1.6f l . obtain the values of c1 and r2 by using fig.32. calculate the value of r1 from the value of c1 and the product r1c1. pll conditions with no signal at pin sig_in pc1 vco adjusts to f c with f pc_in =90 and v vco_in = 0.5v cc . pc2 vco adjusts to f offset with f pc_in = - 360 and v vco_in = minimum.
2003 oct 30 27 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a mga938 f vco f max f c f min 1.1 v 0.5 v cc v cc v cc - 1.1 v vco_in 2f l due to r1,c1 0.6f l f off f vco f max f c f min 1.1 v vco_in 2f l due to r1,c1 due to r2,c1 mga939 0.5 v cc v cc v cc - 1.1 v fig.29 frequency characteristic of vco. b. operating with offset; f c = centre frequency; 2f l = frequency lock range. a. operating without offset; f c = centre frequency; 2f l = frequency lock range.
2003 oct 30 28 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a filter design considerations for pc1 and pc2 of the 74hct9046a figure 30 shows some examples of passive and active filters to be used with the phase comparators of the 74hct9046a. transfer functions of phase comparators and filters are given in table 3. table 3 transfer functions of phase comparators and ?lters. general design consideration. phase comparator explanation figure filter type transfer function pc1 30a. passive ?lter without damping t 1 =r3 c2; t 2 =r4 c2; t 3 =r4 c3; a=10 5 = dc gain amplitude 30b. passive ?lter with damping 30c. active ?lter with damping pc2 t 1 = r3' c2; t 2 =r4 c2; t 3 =r4 c3; r3' = r b /17; r b =25to250k w 30d. passive ?lter with damping a=10 5 = dc gain amplitude 30e. active ?lter with damping a=10 5 = dc gain amplitude subject phase comparator design consideration pll locks on harmonics at centre frequency pc1 yes pc2 no noise rejection at signal input pc1 high pc2 low ac ripple content when pll is locked pc1 f r =2f i ; large ripple content at f pc_in =90 pc2 f r =f i ; small ripple content at f pc_in =0 k pc1 v cc p ---------- - vr = f j w () 1 1j wt 1 + --------------------- = f j w () 1j wt 2 + 1j wt 1 t 2 + () + ------------------------------------- - = f j w () 1j wt 2 + 1a j wt 1 + ----------------------------- = 1j wt 2 + j wt 1 --------------------- ? k pc2 5 4 p ------ - vr = f j w () 1j wt 2 + 1a j wt 1 + ----------------------------- = 1j wt 2 + j wt 1 --------------------- ? f j w () 1j wt 2 + 1a j wt 1 + ----------------------------- = 1j wt 2 + j wt 1 --------------------- ?
2003 oct 30 29 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a mbd107 - 1 x 1/ t r3 c2 f (j w ) r3 c2 c3 r4 c3 a r4 c2 r3 r3' c2 r4 ar3' a c3 r4 c2 o t x 2 1 t 1 t 2 o t x 2 1/ t 2 1/ t 3 1/ o t x 2 1/ a t 1/ 1 o t x 2 1/ a t 1/ 1 a 1/ t 2 1/ t 3 1/ t 1 a a 1/ t 2 1/ t 3 t 1 1/a a 1/ t 2 1/ t 3 circuit amplitude characteristic pole zero diagram 1/ t 1 1 t 1 t 2 1/ 1/ t 1 a pc2 pc1 t 1 1/a r3' 1/ f (j w ) fig.30 passive and active filters for 74hct9046a. a. b. c. d. e.
2003 oct 30 30 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a fig.31 typical value of vco centre frequency (f c ) as a function of c1. 10 7 10 5 10 4 10 3 10 1 10 5 10 3 10 10 2 10 4 10 6 10 6 c1 (pf) 10 7 10 8 (hz) f c 10 2 mbd103 - 1 v = cc 5.5 v 4.5 v w r1 = 3 k r1 = 10 k w r1 = 150 k w r1 = 300 k w 5.5 v 4.5 v 5.5 v 4.5 v 5.5 v 4.5 v r2 = ; v vco_in = 0.5v cc ; inh = gnd; t amb =25 c.
2003 oct 30 31 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a fig.32 typical value of frequency offset as a function of c1. 10 7 10 5 10 4 10 3 10 1 10 5 10 3 10 10 2 10 4 10 6 10 6 c1 (pf) 10 7 10 8 (hz) f off 10 2 mbd104 r2 = 150 k w r2 = 300 k w r2 = 3 k w r2 = 10 k w v = cc 4.5 v - 5.5 v 4.5 v - 5.5 v 4.5 v - 5.5 v 4.5 v - 5.5 v r1 = ; v vco_in = 0.5v cc ; inh = gnd; t amb =25 c.
2003 oct 30 32 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a fig.33 typical frequency lock range 2f l as a function of the product r1 and c1. v vco_in = 1.1 to (v cc - 1.1) v k v 2f l v vco_in range -------------------------------------- 2 p rs v () = 10 7 10 5 10 3 10 10 2 10 4 10 6 r1c1 (s) 10 7 10 8 (hz) 2f l mbd105 - 1 v = cc 10 6 10 5 10 4 10 3 10 2 10 1 1 5.5 v 4.5 v
2003 oct 30 33 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a pll design example the frequency synthesizer used in the design example shown in fig.34 has the following parameters: output frequency: 2 mhz to 3 mhz. frequency steps: 100 khz. settling time: 1 ms. overshoot: <20%. the open loop gain is: h (s) g (s) = k p k f k o k n and the closed loop: where: k p = phase comparator gain k f = low-pass filter transfer gain k o =k v /s vco gain k n = 1 n divider ratio. the programmable counter ratio k n can be found as follows: the vco is set by the values of r1, r2 and c1; r2 = 10 k w (adjustable). the values can be determined using the information in table 2. with f c = 2.5 mhz and f l = 500 khz this gives the following values (v cc = 5.0 v): r1 = 30 k w . r2 = 30 k w . c1 = 100 pf. the vco gain is: the gain of the phase comparator pc2 is: using pc2 with the passive filter as shown in fig.34 results in a high gain loop with the same performance as a loop with an active filter. hence loop filter equations as for a high gain loop should be used. the current source output of pc2 can be simulated then with a fictive filter resistance: the transfer functions of the filter is given by: where: t 1 = r3' c2. t 2 =r4 c2. the characteristic equation is: this results in: or: this can be written as: with the natural frequency w n defined as: and the damping value given as: in fig.35 the output frequency response to a step of input frequency is shown. the overshoot and settling time percentages are now used to determine w n . from fig.35 it can be seen that the damping ratio z = 0.707 will produce an overshoot of less than 20% and settle to within 5% at w n t = 5. the required settling time is 1 ms. this results in: . f u f i ------ - k p k f k o k n 1k p k f k o k n + ----------------------------------------------------- - = n min f out f step ----------- - 2 mhz 100 khz --------------------- - 20 == = n max f out f step ----------- - 3 mhz 100 khz --------------------- - 30 == = k v 2f l 2 p v cc 1.1 C () 1.1 C -------------------------------------------- 1 mhz 2.8 ---------------- - 2 p 2.24 10 6 rs v ? == k p 5 4 p ------------ 0.4v r == r3' r b 17 ------ - = k f 1s t 2 + s t 2 ------------------ = 1k p k f k o k n + 1k p 1s t 2 + s t 1 ------------------ ? ?? k v s ----- - k n 0 = + s 2 sk p k v k n t 2 t 1 ---- - k p k v k n t 1 0 = ++ s 2 2 zw n s w n () 2 + + 0 = w n k p k v k n t 1 -------------------------------- = z 0.5 t 2 w n = w n 5 t -- - 5 0.001 -------------- - 510 3 rs == =
2003 oct 30 34 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a rewriting the equation for natural frequency results in: the maximum overshoot occurs at n max = 30; hence k n = 1 30 : when c2 = 470 nf, it follows: hence the current source bias resistance r b =17 2550 = 43 k w . with z = 0.707 (0.5 t 2 w n ) it follows: for extra ripple suppression a capacitor c3 can be connected in parallel with r4, with an extra t 3 =r4 c3. for stability reasons t 3 should be < 0.1 t 2 , hence c3 < 0.1c2 or c3 = 39 nf. t 1 k p k v k n w n () 2 -------------------------------- = t 1 0.4 2.24 10 6 5000 2 30 ----------------------------------------- - 0.0012 == r3 t 1 c2 ------- - 0.0012 470 10 9 C --------------------------- - 2550 w == = t 2 0.707 0.5 5000 --------------------------- - 0.00028 == r4 t 2 c2 ------- - 0.00028 470 10 9 C --------------------------- - 600 w == = mbd098 r4 c2 r2 r1 vco r3' phase comparator pc2 divide by 10 "190" oscillator "hcu04" 13 100 khz 14 3 4 f out programmable divider "4059" 9 11 12 6 7 5 1 mhz k p k n k f k o c1 c3 (1) r 15 b f u fig.34 frequency synthesizer. (1) r3' fictive resistance = r3' r b 17 ------ - = c1 = 100 pf. c2 = 470 nf. c3 = 39 nf. r1 = 30 k w . r2 = 30 k w . r3' = 2550 w . r b =43k w . r4 = 600 w .
2003 oct 30 35 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a 012 4 1.6 1.0 0.6 0 0.8 mga959 3 1.4 1.2 0.4 0.2 5678 w n t dw (t) e dw e / w n df (t) e df e / w n - 0.6 0 0.4 1.0 0.2 - 0.4 - 0.2 0.6 0.8 = 5.0 z 0.5 0.707 1.0 = 0.3 z = 2.0 z fig.35 type 2, second order frequency step response. since the output frequency is proportional to the vco control voltage, the pll frequency response can be observed with an oscilloscope by monitoring pin vco_in of the vco. the average frequency response, as calculated by the laplace method, is found experimentally by smoothing this voltage at pin vco_in with a simple rc filter, whose time constant is long compared with the phase detector sampling rate but short compared with the pll response time. further information for an extensive description and application example please refer to application note ordering number 9397 750 00078. mga952 3.1 3.0 2.9 2.1 2.0 1.9 0 0.5 1.0 1.5 2.0 2.5 time (ms) proportional to output frequency (mhz) n = 30 n stepped from 29 to 30 step input n stepped from 21 to 20 fig.36 frequency compared to the time response.
2003 oct 30 36 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a package outlines unit a max. 1 2 b 1 cee m h l references outline version european projection issue date iec jedec jeita mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot38-1 99-12-27 03-02-13 a min. a max. b max. w m e e 1 1.40 1.14 0.055 0.045 0.53 0.38 0.32 0.23 21.8 21.4 0.86 0.84 6.48 6.20 0.26 0.24 3.9 3.4 0.15 0.13 0.254 2.54 7.62 0.3 8.25 7.80 0.32 0.31 9.5 8.3 0.37 0.33 2.2 0.087 4.7 0.51 3.7 0.15 0.021 0.015 0.013 0.009 0.01 0.1 0.02 0.19 050g09 mo-001 sc-503-16 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 16 1 9 8 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. (1) (1) d (1) z dip16: plastic dual in-line package; 16 leads (300 mil); long body sot38-1
2003 oct 30 37 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot109-1 99-12-27 03-02-19 076e07 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1
2003 oct 30 38 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot403-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 18 16 9 q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 a max. 1.1 pin 1 index
2003 oct 30 39 philips semiconductors product speci?cation pll with band gap controlled vco 74hct9046a data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
? koninklijke philips electronics n.v. 2003 sca75 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands r44/05/pp 40 date of release: 2003 oct 30 document order number: 9397 750 12178

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